Tackling low ATPG test coverage in Tessent DFT

Chips today are becoming increasingly complex. Encountering millions of flops per design block has become a common occurrence in todays SoCs. High test coverage of these designs directly correlates to the quality of the ICs shipped and hence the semiconductor companies strive to achieve highest test coverage. For instance, ICs designed for life-critical applications such as autonomous driving requires DPPM to be zero.