Microsoft - HLS Hardware Design Patterns

High-Level Synthesis (HLS) using untimed C++ presents an elegant hardware abstraction framework for simplifying hardware design at the unit level. To construct large designs in untimed C++, the design needs to be broken down into isolated units connected via channels. The process of breaking down a design into units usually ends up being more than simply dividing modules, there are specific design considerations that need to be considered in this process in order to produce a design that will function correctly in a system after RTL is generated.

This presentation discusses some core considerations for partitioning a digital design and introduces a basic set of HLS Hardware Design Patterns that provide foundational and conceptual building blocks for large-scale designs. Generic design patterns for common design aspects such as interfaces, input, and output arbitration, configuration, and flushing will be covered.