LVS debug of today’s complex designs is challenging and time-consuming, but reducing LVS debug time while continuing to provide reliable, high-performance designs is a requirement for chip designers who want to meet their tight tapeout deadlines and satisfy customers.
Siemens EDA is providing new techniques and tools that work together to automated and enhance LVS debugging capabilities, ensuring that their customers can meet market deadlines while maintaining product quality, even for the most advanced designs.
Layout vs. schematic (LVS) comparison is often a
tedious and time-consuming process, requiring many debugging
iterations and cross-functional interactions before a designer team
converges to a LVS-clean design.
Siemens EDA is responding with new LVS technology to
help designers more quickly and efficiently converge to a LVS-clean
design.
What’s emerging are comprehensive LVS debug solutions
that can help designers quickly identify and resolve LVS errors. The
ideal debug solution would address the two critical issues currently
impacting the LVS process of advanced node design verification:
Let’s take a closer look at why those issues exist, and then we’ll
examine some of the new LVS technology helping to resolve them.