Codasip: Building an RTL-to-GDS Flow for a High Performance RISC-V Design
While P&R evaluations and SoC flow development are an extremely costly exercise, companies also have the challenge of securing enough engineering resources to implement their complex designs. For Codasip, Europe’s leading RISC-V processor solution company, developing RISC-V soft-IP that must meet the highest performance targets, requires a robust and predictable implementation flow, and a trusted partner that can not only provide tool solutions but also the know-how. Codasip turned to Siemens EDA for their RTL-to-GDSII flow that delivers industry standard PPA performance, time-after-time, and partnered with Siemens Design Services to implement their RISC-V IP. In this presentation, Codasip will show how Siemens DS was able to take their complex and demanding requirements , deliver a proposal, and execute the project to plan, maintaining clear communications throughout, and ultimately meeting the PPA objectives. The resulting high quality flow is being used to reliably deliver virtual tapeout results to Codasip customers on their customizable RISC-V IP.
Seznamte se s přednášejícím
Athanasios Grassos
Physical Design Manager
Athanasios (a.k.a Thanos) Grassos is a Physical Design Manager at Codasip, working on RISC-V customizable processors. He earned his Diploma in Electrical and Computer Engineering, from the University of Patras, Greece. Thanos then earned his Master’s in Electronics Design at the University of Glasgow, followed by a Master’s in Mathematics from Birkbeck University of London. He has worked as a Physical Design engineer since 2012, at companies like Imagination's Technology, Broadcom, and ARM, among others. He has expertise on all aspects of the RTL-to-GDSII flow, with multiple tapeout experiences on state-of-the-art process nodes.