Early Power convergence is important for timely chip closure as well as eventual system thermals closure. We utilized the capabilities within Powerpro in combination with the Veloce Emulation platform’s Power App to perform early RTL level power trend analysis and optimization guidance. Effective power analysis and optimization of large SoCs requires simulation vectors that reflect real scenarios and workloads. However, these vectors are very often difficult to obtain when developing individual blocks and IP’s in an SoC. They do, however, exist in full SoC emulation runs that apply realistic workloads; especially for time windows exhibiting peak activity of these workloads. In this presentation, we will share the methodology and the results of our integrated flow that uses the Veloce Power App to identify peak activity intervals which in turn, drive PowerPro’s power analysis, key performance metric reporting, and guided / automatic RTL power optimization. PowerPro’s power analysis has a direct API integration into the waveform data coming from the Veloce Power App to minimize time to power using such large datasets. We will then describe our power optimization flow where we use PowerPro with FSDB format waveforms which are generated from the Veloce time windows using a utility. This flow (both guided and automatic) allows us to increase power efficiency and identify power reduction opportunities of 5% (across the digital design) early in the design cycle and enables us to effectively deliver lower power RTL. (Presented at U2U 2020)
Meet the speakers
Sr. Tech Lead
Udupi Harisharan has worked on Networking Asics for the past 20 years taping out more than 15 Asics and Leads a team Focused on design and implementation including Asic Design methodologies involving Soc integration, Power optimization, Power Analysis and Emulation of the Data center Asics at Cisco.
Sai Rama Krishna Nalla
ASIC Hardware Engineer
Sai Rama Krishna Nalla achieved his Masters degree in electrical engineering in May 2019 from San Jose State University. He is part of the data center networking group at Cisco, working on power analysis and optimization, top level formal verification of ASIC chip.