Ensuring adequate ESD protection is an extremely important aspect of integrated circuit (IC) design and physical verification. There are well-established design and automated verification strategies for 2D ICs, but 2.5D and 3D IC integration present new challenges in both design and verification. While there are several design methodologies focused on implementing effective ESD protection in 2.5D and 3D ICs, EDA solutions for automated verification of these protection schemes are less readily available. However, there is one proven solution in use today.
In this webinar, we define the unique ESD protection verification challenges introduced by 2.5/3D IC integration technologies and explain how to select the appropriate ESD protection scheme for different parts of 2.5/3D IC designs. We introduce an automated verification methodology for 2.5D and 3D ICs, based on the Calibre PERC reliability platform, that provides accurate and consistent verification of ESD protection structures across and within 2.5/3D IC package designs.
What you will learn:
Understand unique ESD protection verification challenges associated with 2.5D/3D IC designs
Ensure adequate ESD protection in 2.5/3D IC designs that incorporate different technology nodes and design methodologies
Optimize the use of chip area by placing the appropriate ESD protection
Improve ESD robustness in 2.5/3D designs with more accurate and consistent ESD protection verification