Webinar
Advance your Designs with Advances in CDC and RDC
On-demand
Overview:
In this 30 minute session you will gain an understanding of valuable new capabilities available in Questa CDC, RDC and Signoff CDC that are important to leverage early and often in development to ensure working and error-free multi-clock and reset designs.
What You Will Learn:
- How to improve your analysis turnaround time with causality reporting
- A flow to implement constraint validation
- The value of catching not only datapath glitches in CDCs but also clock and reset glitches
- How to implement your analysis on either Linux or Windows with Siemens’ new UI
Who Should Attend:
- Design & Verification Engineers & Managers
Meet the speakers
Siemens EDA
Kurt Takara
Lead Product Engineer
Kurt Takara is the Lead Product Engineer for Questa CDC+RDC at Siemens EDA, and has over 20 years of experience in engineering design and verification, technical marketing and engineering services. Takara has held engineering, marketing, consulting services and project management roles in electronics and EDA companies such as 0-In Design Automation, Synopsys, Ikos Systems, Raytheon and Magnavox. He holds a BSEE from Purdue University and an MBA from Santa Clara University.
Siemens EDA
Ping Yeung
Principal Engineer
Ping Yeung, Ph.D. is the Principal Engineer in Siemens EDA. He has over 20 years application, marketing, and product development experience in the EDA industry, including positions at 0-In, Synopsys, and Mentor. He holds 7 patents in the CDC and formal verification areas.
Siemens EDA
Chris Giles
Design Solutions Product Manager
Chris is a member of the DVT Product Marketing team, managing the Design Solutions product line, including the CDC+RDC product lines as well as the HDL Designer Series. Chris comes to Siemens EDA from the user community, with decades of experience in IP and ASIC/SoC/FPGA R&D and management, with products deployed in consumer, military, compute and storage markets and at companies such as Hewlett Packard Enterprise, Honeywell, Seagate, Micron, NEC and LSI Logic. The author of 18 patents in areas such as hardware virtualization, security, processor architecture, synchronization schemes, and hardware prototyping, Chris received an MSEE from Stanford University in California and a BSEE from Rice University in Texas.