In this 30 minute session you will gain an understanding of valuable new capabilities available in Questa CDC, RDC and Signoff CDC that are important to leverage early and often in development to ensure working and error-free multi-clock and reset designs.
What you will learn:
How to improve your analysis turnaround time with causality reporting
A flow to implement constraint validation
The value of catching not only datapath glitches in CDCs but also clock and reset glitches
How to implement your analysis on either Linux or Windows with Siemens’ new UI
Who should attend:
Design & Verification Engineers & Managers