Webinar

A Guide to QVIP Workflow and Debug for PCIe

On-demand

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Overview:

Developing a testbench with complex Verification IP components is a monumental task taking up many weeks and multiple iterations in the verification cycle of a SoC development project. QVIP Configurator is a Graphical User Interface based tool aimed at providing a jump start for building a complete ready-to-use testbench for Questa Verification IP with the ability to re-use components into an existing testbench. QVIP Configurator provides the ability to instantiate, connect and configure multiple different QVIPs components in a single session thereby providing the end-user a complete testbench for verifying their SoC.

This session walks through the step-by-step workflow to integrate Questa VerificationIP (QVIP) - PCIe into a testbench. The workflow demonstrates a jump start guide on developing a complete working testbench using QVIP, thereby reducing the testbench development efforts, and also the efforts needed for integrating QVIP into an existing testbench. The workflow highlights key strides which dramatically reduces the integration efforts from weeks down to few hours allowing Verification Engineers to be more productive during their verification cycle.

What You Will Learn:

  • The workflow of integrating a Verification IP into a testbench.
  • Ease of use on developing a complete testbench using QVIP PCIe with the ability to configure the QVIP based on the Design requirements.
  • The advance debug capabilities of QVIP PCIe provides detailed visibility and record of TLPs and DLLPs exchanged over the PCIe link.

 Who Should Attend:

  • Design & Verification Engineers & Managers and those developing complex testbenches for SoC Verification using standard Verification IP components.

Meet the speakers

Photo of Akshay Sarup
Siemens EDA

Akshay Sarup

CXL & PCIe Product Engineer

Akshay Sarup is a Product Engineer for CXL and PCIe at Siemens EDA, focusing on deployment and product definition of Questa Verification IP. Sarup has over 20 years of experience in the functional verification domain, with a background in developing industry standard interface protocols using the UVM methodology.
Photo of Tom Fitzpatrick
Siemens EDA

Tom Fitzpatrick

Strategic Verification Architect

Tom is a Strategic Verification Architect at Siemens Digital Industries Software (Siemens EDA) where he works on developing advanced verification methodologies and educating users and partners on their adoption. He has been a significant contributor to several industry standards, both in Accellera and IEEE, including Verilog 1364, SystemVerilog 1800, UVM 1800.2 and is a founding member and current Vice-Chair of the Portable Stimulus Working Group. He is also the 2019 recipient of the Accellera Technical Excellence Award. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification, Portable Stimulus, and other functional verification topics and has produced some of the most popular and successful video training courses on Mentor's Verification Academy website. Tom holds Master’s and Bachelor’s degrees in EE/CS from MIT, is an avid golfer and a huge Boston Red Sox and New England Patriots fan, and has been married to his wife, Dee, for 25 years.

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