On-Demand Webinar

A Guide to QVIP Workflow and Debug for PCIe

Estimated Watching Time: 29 minutes

Share

Developing a testbench with complex Verification IP components is a monumental task taking up many weeks and multiple iterations in the verification cycle of an SoC development project. QVIP Configurator is a Graphical User Interface-based tool aimed at providing a jump start for building a complete ready-to-use testbench for Questa Verification IP with the ability to re-use components into an existing testbench.

QVIP Configurator provides the ability to instantiate, connect and configure multiple different QVIPs components in a single session thereby providing the end-user a complete testbench for verifying their SoC.

Integrate Questa Verification IP (QVIP) - PCIe into a testbench.

The workflow demonstrates a jump start guide on developing a complete working testbench using QVIP, thereby reducing the testbench development efforts, and also the efforts needed for integrating QVIP into an existing testbench. The workflow highlights key strides which dramatically reduces the integration efforts from weeks down to few hours allowing Verification Engineers to be more productive during their verification cycle.

What You Will Learn:

  • The workflow of integrating a Verification IP into a testbench.

  • Ease of use on developing a complete testbench using QVIP PCIe with the ability to configure the QVIP based on the Design requirements.

  • The advance debug capabilities of QVIP PCIe provides detailed visibility and record of TLPs and DLLPs exchanged over the PCIe link.

Who Should Attend:

  • Design & Verification Engineers & Managers and those developing complex testbenches for SoC Verification using standard Verification IP components.

Meet the speaker

Siemens EDA

Akshay Sarup

Verification Technologist

Akshay Sarup is Verification Technologist for Siemens EDA Design Verification Technology Division. He has extensive experience in Verification IP deployment and development. He is an expert in protocols like PCIe, NVMe, Ethernet, AMBA family and has over 17 years of experience in Design Verification Software development.