Learn how Dream Chip reduced power and improved turnaround time with Aprisa

Learn about Aprisa Digital IC Implementation from real users.

At the 2023 User2User symposium, customers gathered to share their experience with Siemens EDA tools solutions, including in the digital implementation space.

In this presentation, Cas Groot, Director of SoC Engineering at Dream Chip, presented "Reducing Power and Improving Turnaround Time” using Aprisa digital implementation.

How Dream Chip improved IC design efficiency

Dream Chip is Germany’s largest independent engineering service provider focusing on the development and design of ASICs, SoCs, FPGAs, embedded software and discrete systems.

Accelerate IC design turnaround time with Aprisa

• Best-in class PPA and fast turnaround time out-of-the-box, including minimal setup effort for CTS.
• Good quality of results due to Aprisa’s detail-route-centric approach that achieves excellent correlation pre- and post-route, giving Dream Chip designers early insights about congestion hotspots in a memory dominated design.
• Reduced power consumption without the need of endless ECOs that can be costly in terms of time-to-market.

Watch this on demand video to learn how your design teams can take advantage of Aprisa’s ease-of-use while achieving optimal PPA and fast TAT.

To learn more about how Aprisa digital implementation solution delivers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs, visit our web page.